Hackaday

FPGAs In C With Cynth

Programming an FPGA with Verilog looks a lot like programming. But it isn’t, at least not in the traditional sense. There have been several systems that aim to take C code and convert it into a ...
EDN

Assertion Methodologies for Verilog Design

Sometimes good ideas take a while to catch on in engineering practice. The use of in-line assertions to document assumptions and check for problems in RTL code is one such idea. Long ago proposed for ...
Design-Reuse

Guidelines for Verilog-A Compact Model Coding

The Verilog-AMS hardware description language [1] includes extensions dedicated to compact modeling, but does not define a reserved subset for compact modeling. This lack of specification combined ...
EDN

‘Obfuscators’ render Verilog, VHDL unreadable

Santa Cruz, Calif. — Providing a new approach to intellectual property (IP) protection, software engineering firm Semantic Designs has released production-quality “obfuscators” for Verilog 2001 and ...
Linux Journal

Open Source in Electronic Design Automation

The world of open-source software is making inroads into areas beyond operating systems, Internet and desktop applications, GUIs and scripting languages. One less well-known area of open-source ...
Embedded

Implementing an Enhanced Rate Multiplier in your embedded systems design

In many embedded communications and networking applications it is oftennecessary to derive fractional frequencies from some common baselinefor use in particular applications. In communications ...